The RAPSIZE definition originally introduced in 9c07a7af5da: "target/i386: Expose new feature bits in..." hard-coded the value of the field to 0x8. While this value works for current CPUs, the value may change in the future. Update the definition to be a bit-mask instead of a hard-coded value for future-proofing.
The field is currently unused, so no functional change is intended. Signed-off-by: Ben Cheatham <[email protected]> --- target/i386/cpu.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e66333cd9c24..ff63baa9dd23 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1214,10 +1214,11 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO (1U << 30) /* - * Return Address Predictor size. RapSize x 8 is the minimum number of - * CALL instructions software needs to execute to flush the RAP. + * Return Address Predictor size. RapSize x Y is the minimum number of + * CALL instructions software needs to execute to flush the RAP, where + * Y is the value of CPUID_8000_0021.EBX[23:16]. */ -#define CPUID_8000_0021_EBX_RAPSIZE (8U << 16) +#define CPUID_8000_0021_EBX_RAPSIZE (0x00FF0000U) /* CPU is not vulnerable TSA SA-SQ attack */ #define CPUID_8000_0021_ECX_TSA_SQ_NO (1U << 1) -- 2.53.0
