On Wed, Jul 1, 2026 at 7:11 AM Daniel Henrique Barboza <[email protected]> wrote: > > riscv-iommu spec: "If SADE is 1, the IOMMU updates A and D bits in > first-stage PTEs atomically. If SADE is 0, the IOMMU causes a > page-fault corresponding to the original access type if the > A bit is 0 or if the memory access is a store and the D bit is 0.". > > Note that SADE=0 and A=0 will always cause a fault regardless of the > original access type. Right now we're faulting in this case just for > reads. > > Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3551 > Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > hw/riscv/riscv-iommu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index c9687e01a8..70eede3f14 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -480,7 +480,7 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, > RISCVIOMMUContext *ctx, > break; /* Read access check failed */ > } else if ((iotlb->perm & IOMMU_WO) && !(pte & PTE_W)) { > break; /* Write access check failed */ > - } else if ((iotlb->perm & IOMMU_RO) && !ade && !(pte & PTE_A)) { > + } else if (!ade && !(pte & PTE_A)) { > break; /* Access bit not set */ > } else if ((iotlb->perm & IOMMU_WO) && !ade && !(pte & PTE_D)) { > break; /* Dirty bit not set */ > -- > 2.43.0 > >
