From: Daniel Henrique Barboza <[email protected]>
Seems like we forgot to add a flag to set satp-mode=bare. What we're
doing instead is to set the CPU default satp-mode to 'off' to set it to
bare ... assuming we know the default satp-mode. Otherwise one needs to
do -cpu X,sv39=off,sv48=off,sv57=off,sv64=off to get a bare-mode CPU.
Add a flag to make this process easier. The name choice is based on the
fact that I didn't find many references to 'mbare' in RISC-V docs, but
'svbare' is a flag name that toolchain uses to set satp-mode=bare.
Might as well use the same name to help with cross project compat.
After this patch:
$ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb -cpu rv64
$ dtc -I dtb -O dts fdt.dtb | grep mmu-type
mmu-type = "riscv,sv57";
$ ./build/qemu-system-riscv64 -M virt,dumpdtb=fdt.dtb -cpu rv64,svbare=on
$ dtc -I dtb -O dts fdt.dtb | grep mmu-type
mmu-type = "riscv,none";
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
---
target/riscv/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e16608bbbe..bff3ed5de1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -418,7 +418,7 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc)
#ifndef CONFIG_USER_ONLY
static uint8_t satp_mode_from_str(const char *satp_mode_str)
{
- if (!strncmp(satp_mode_str, "mbare", 5)) {
+ if (!strncmp(satp_mode_str, "svbare", 6)) {
return VM_1_10_MBARE;
}
@@ -1063,6 +1063,9 @@ void riscv_add_satp_mode_properties(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
+ object_property_add(obj, "svbare", "bool", cpu_riscv_get_satp,
+ cpu_riscv_set_satp, NULL, &cpu->satp_modes);
+
if (cpu->env.misa_mxl == MXL_RV32) {
object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
cpu_riscv_set_satp, NULL, &cpu->satp_modes);
--
2.54.0
