On Wed, Jun 10, 2026 at 06:41:28PM +0800, Daniel Henrique Barboza wrote:
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support and others.
>
> We're going for a profile-based implementation, instead of a regular CPU
> that can inherit RVA23, to allow future CPUs to use it internally as a
> starting base for their own extension sets. There's also a new
> 'rvserver-ref-1.0' flag that can be used to set the extensions in the
> command line for other CPUs, which can be used for testing/debugging
> purposes.
>
> Note that for all intents and purposes "riscv-server-ref" is a regular
> CPU and no, we're not trying to set a precedent of calling the riscv
> server platform spec a profile.
>
> [1] defines in rule SEE_020 that we must support at least 11 debug
> triggers (4 for insn address, 4 for insn load/store, 1 for icount,
> one for int, one for excp). We're going for the minimum. If more
> triggers are needed users can set any trigger amount with:
>
> -cpu riscv-server-ref,trigger-count=N
>
> Note that N must be <= 128.
>
> [1]
> https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc
>
> Suggested-by: Icenowy Zheng <[email protected]>
> Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 30dcdcfaae..a150acd151 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -42,6 +42,7 @@
> #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
> #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
> #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
> +#define TYPE_RISCV_CPU_RVSERVER_REF
> RISCV_CPU_TYPE_NAME("riscv-server-ref")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e02d53cbba..63fbc4b98e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2063,11 +2063,35 @@ static RISCVCPUProfile RVA23S64 = {
> }
> };
>
> +/*
> + * The riscv-server-ref spec isn't a profile per se but its
> + * CPU definition can be modelled as a profile that extends
> + * RVA23, with additional things on top of it, and allowing
> + * future CPUs to derive from it via
> + * ".profile = &RVServerRef1_0;".
> + */
> +static RISCVCPUProfile RVServerRef1_0 = {
> + .s_parent = &RVA22S64,
> + .name = "rvserver-ref-1.0",
> + .satp_mode = VM_1_10_SV48,
> + .ext_offsets = {
> + CPU_CFG_OFFSET(ext_zkr),
> + CPU_CFG_OFFSET(ext_sdtrig),
> + CPU_CFG_OFFSET(ext_ssaia),
> + CPU_CFG_OFFSET(ext_ssccfg),
> + /* ssstrict is always enabled for PRIV_VER_1_12 */
> +
> + RISCV_PROFILE_EXT_LIST_END
> + }
> +};
> +
> +
> RISCVCPUProfile *riscv_profiles[] = {
> &RVA22U64,
> &RVA22S64,
> &RVA23U64,
> &RVA23S64,
> + &RVServerRef1_0,
> NULL,
> };
>
> @@ -3326,6 +3350,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #endif
> ),
>
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU,
> + .profile = &RVServerRef1_0,
> + .misa_mxl_max = MXL_RV64,
> + .cfg.max_satp_mode = VM_1_10_SV57,
> + .num_triggers = 11,
> + ),
> +
> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
> .cfg.max_satp_mode = VM_1_10_SV57,
> --
> 2.43.0
>
