On Thu, Jul 2, 2026 at 8:54 PM Michael Tokarev <[email protected]> wrote: > > On 01.07.2026 13:17, [email protected] wrote: > ... > > RISC-V PR for 11.1 > > > > * Fix IMSIC CSR write and add tests > > * Parametrise debug trigger number > > * Add 'svbare' satp-mode > > * Fix RINTC PLIC context ID for KVM > > * Avoid abort when reading vtype before env->xl is set > > * Skip reset for KVM irqchip > > * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE > > * More FDT cleanups (PLIC) > > * Make FCTL.BE in IOMMU read only 0 > > * Check DC.TC reserved bits in IOMMU > > * Apply UXL WARL handling to vsstatus > > * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU > > * Set RISCV_IOMMU_FQ_HDR_PV appropriately > > * Fix MSI MRIF IOMMU interrupt-pending offset > > * Report QEMU CPU archid as 42 > > * Check PMP before updating PTE > > * Add the Tenstorrent Atlantis machine > > > > ---------------------------------------------------------------- > > Alistair Francis (1): > > hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr > > > > Charlie Jenkins (1): > > target/riscv: Report QEMU CPU archid as 42 > > > > Chris Rauer (1): > > hw/i2c: Add DesignWare I2C Controller > > > > Daniel Henrique Barboza (16): > > target/riscv/cpu: add CPU unrealize callback > > target/riscv: dynamic alloc of debug trigger arrays > > target/riscv: add 'num-triggers' debug property > > target/riscv/cpu.c: add 'svbare' satp-mode > > hw/riscv/sifive_u.c: remove unneeded qemu_fdt_get_phandle() call > > hw/riscv/sifive_u.c: use intc_phandle in plic creation > > hw/riscv/sifive_u: add #address-cells in PLIC FDT > > hw/riscv/virt.c: change 'plic' nodename to 'interrupt-controller' > > hw/riscv: add create_fdt_plic() helper > > hw/riscv/riscv-iommu: rename regs_rw to regs > > hw/riscv/riscv-iommu.c: make FCTL.BE read only 0 > > hw/riscv/riscv-iommu: check DC.TC reserved bits > > hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set > > hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately > > hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset > > hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0 > > > > Inochi Amaoto (1): > > target/riscv: Check PMP before updating PTE > > > > Joel Stanley (9): > > target/riscv: Avoid NULL deref in IMSIC CSR write > > tests/functional/riscv64: Use newer kernel for tuxrun boot > > tests/functional/riscv64: Add virt machine AIA boot test > > hw/riscv/virt: Move AIA initialisation to helper file > > hw/riscv/aia: Provide number of irq sources > > hw/riscv/aia: Configure stride for the M-mode IMSIC > > hw/riscv: Add Tenstorrent Atlantis machine > > hw/riscv/atlantis: Integrate i2c controllers > > hw/riscv/atlantis: Add some i2c peripherals > > > > Meng Zhuo (1): > > target/riscv/kvm: skip FP/Vector sync on KVM_PUT_RUNTIME_STATE > > > > Nicholas Piggin (4): > > hw/riscv/boot: Describe discontiguous memory in boot_info > > hw/riscv/boot: Account for discontiguous memory when loading firmware > > target/riscv: tt-ascalon: Enable Zkr extension > > tests/functional/riscv64: Add tt-atlantis tests > > > > Qingwei Hu (3): > > hw/riscv/virt-acpi-build: Fix RINTC PLIC context ID for KVM > > hw/intc: riscv_aplic: Skip reset for KVM irqchip > > hw/intc: riscv_imsic: Skip reset for KVM irqchip > > > > SeungJu Cheon (1): > > target/riscv: Apply UXL WARL handling to vsstatus > > > > ZhengXiang Qin (1): > > target/riscv: avoid abort when reading vtype before env->xl is set > > > Hi! > > Is there anything here worth picking up for the stable series > (besides "target/riscv: Check PMP before updating PTE")? > > For example, > > 46d96da130 target/riscv: avoid abort when reading vtype before env->xl > is set > 5a3fd18f4f hw/riscv/riscv-iommu.c: make FCTL.BE read only 0 > 13c2fc34f1 hw/riscv/riscv-iommu: check DC.TC reserved bits > 6ed77682d5 hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set > 887d2d75b1 hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately > 3cee183ff9 hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset > 64ce9ac187 hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0 > > resolves various bugs from the qemu issue/work-items tracker.
Everything with a Fixes tag should be backported to releases that have the relevant commits Alistair > > Thanks, > > /mjt
