On 6/10/2026 2:13 AM, Dongli Zhang wrote:
When xtsup=on is exposed, Linux switches the AMD IOMMU event interrupt setup to x2APIC mode and programs the INTCAPXT event register instead of relying on the PCI MSI capability. QEMU currently neither records writes to the INTCAPXT event register nor uses the programmed event vector when raising an AMD IOMMU event interrupt. As a result, DMA faults can be logged into the event log without delivering the AMD-Vi event interrupt to the guest when xtsup=on. Add the INTCAPXT event MMIO offset and accept guest writes to it. When IntCapXT is enabled, build the AMD-Vi event interrupt MSI message from the programmed INTCAPXT event register; otherwise keep the existing PCI MSI fallback. This patch intentionally only supports the INTCAPXT event interrupt path. It does not add PPR or GA-log interrupt support. Keep command completion wait interrupts on the existing PCI MSI path by using a separate event interrupt helper for INTCAPXT delivery. Send INTCAPXT event interrupts through the APIC MSI delivery hook so KVM can handle x2APIC destination IDs above 255. Signed-off-by: Dongli Zhang <[email protected]> --- hw/i386/amd_iommu.c | 50 +++++++++++++++++++++++++++++++++++++++------ hw/i386/amd_iommu.h | 2 ++ 2 files changed, 46 insertions(+), 6 deletions(-)
Hi Dongli, The fix for this issue is already upstream https://lore.kernel.org/qemu-devel/[email protected]/ You can drop this patch in the next version Thanks Sairaj
