Adjust all uses of 'struct' in the uses of this type.
Signed-off-by: Richard Henderson <[email protected]>
---
include/exec/breakpoint.h | 8 ++++----
include/hw/core/cpu.h | 2 --
include/qemu/typedefs.h | 2 ++
target/arm/cpu.h | 4 ++--
target/i386/cpu.h | 4 ++--
target/ppc/cpu.h | 4 ++--
target/riscv/cpu.h | 4 ++--
target/xtensa/cpu.h | 4 ++--
target/riscv/debug.c | 4 ++--
9 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h
index 4a025edc96..1a3391ac09 100644
--- a/include/exec/breakpoint.h
+++ b/include/exec/breakpoint.h
@@ -27,20 +27,20 @@ typedef int BreakpointFlags;
#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
-typedef struct CPUBreakpoint {
+struct CPUBreakpoint {
vaddr pc;
BreakpointFlags flags;
QTAILQ_ENTRY(CPUBreakpoint) entry;
-} CPUBreakpoint;
+};
-typedef struct CPUWatchpoint {
+struct CPUWatchpoint {
vaddr vaddr;
vaddr len;
vaddr hitaddr;
MemTxAttrs hitattrs;
int flags; /* BP_* */
QTAILQ_ENTRY(CPUWatchpoint) entry;
-} CPUWatchpoint;
+};
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags,
CPUBreakpoint **breakpoint);
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e05e261883..160db776d8 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -84,8 +84,6 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU,
typedef struct ArchCPU CpuInstanceType; \
OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
-typedef struct CPUWatchpoint CPUWatchpoint;
-
/* see physmem.c */
struct CPUAddressSpace;
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 2344c92182..919fe8ebff 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -39,9 +39,11 @@ typedef struct Chardev Chardev;
typedef struct Clock Clock;
typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
typedef struct CPUArchState CPUArchState;
+typedef struct CPUBreakpoint CPUBreakpoint;
typedef struct CPUPluginState CPUPluginState;
typedef struct CPUState CPUState;
typedef struct CPUTLBEntryFull CPUTLBEntryFull;
+typedef struct CPUWatchpoint CPUWatchpoint;
typedef struct DeviceState DeviceState;
typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot;
typedef struct DisasContextBase DisasContextBase;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 84d33e87dc..973522cd55 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -754,8 +754,8 @@ typedef struct CPUArchState {
ARMVectorReg za[ARM_MAX_VQ * 16];
} za_state;
- struct CPUBreakpoint *cpu_breakpoint[16];
- struct CPUWatchpoint *cpu_watchpoint[16];
+ CPUBreakpoint *cpu_breakpoint[16];
+ CPUWatchpoint *cpu_watchpoint[16];
/* Optional fault info across tlb lookup. */
ARMMMUFaultInfo *tlb_fi;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e6a197602d..9dbfa7c9b9 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2185,8 +2185,8 @@ typedef struct CPUArchState {
target_ulong exception_next_eip;
target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
union {
- struct CPUBreakpoint *cpu_breakpoint[4];
- struct CPUWatchpoint *cpu_watchpoint[4];
+ CPUBreakpoint *cpu_breakpoint[4];
+ CPUWatchpoint *cpu_watchpoint[4];
}; /* break/watchpoints for dr[0..3] */
int old_exception; /* exception in flight */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 057c54bbb8..d06f3dfd7f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1320,8 +1320,8 @@ struct CPUArchState {
/* MMU context, only relevant for full system emulation */
#if defined(TARGET_PPC64)
ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
- struct CPUBreakpoint *ciabr_breakpoint;
- struct CPUWatchpoint *dawr_watchpoint[2];
+ CPUBreakpoint *ciabr_breakpoint;
+ CPUWatchpoint *dawr_watchpoint[2];
#endif
target_ulong sr[32]; /* segment registers */
uint32_t nb_BATs; /* number of BATs */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bdd28d329b..9cd38d10a3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -491,8 +491,8 @@ struct CPUArchState {
uint64_t *tdata1;
uint64_t *tdata2;
uint64_t *tdata3;
- struct CPUBreakpoint **cpu_breakpoint;
- struct CPUWatchpoint **cpu_watchpoint;
+ CPUBreakpoint **cpu_breakpoint;
+ CPUWatchpoint **cpu_watchpoint;
QEMUTimer **itrigger_timer;
int64_t last_icount;
bool itrigger_enabled;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 442e98bd1b..ab42b4be00 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -545,9 +545,9 @@ struct CPUArchState {
unsigned static_vectors;
/* Watchpoints for DBREAK registers */
- struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
+ CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
/* Breakpoints for IBREAK registers */
- struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK];
+ CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK];
};
/**
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index b8fea64bec..67c09b1a53 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -1060,8 +1060,8 @@ void riscv_trigger_realize(CPURISCVState *env)
env->tdata1 = g_new0(uint64_t, env->num_triggers);
env->tdata2 = g_new0(uint64_t, env->num_triggers);
env->tdata3 = g_new0(uint64_t, env->num_triggers);
- env->cpu_breakpoint = g_new0(struct CPUBreakpoint *, env->num_triggers);
- env->cpu_watchpoint = g_new0(struct CPUWatchpoint *, env->num_triggers);
+ env->cpu_breakpoint = g_new0(CPUBreakpoint *, env->num_triggers);
+ env->cpu_watchpoint = g_new0(CPUWatchpoint *, env->num_triggers);
env->itrigger_timer = g_new0(QEMUTimer *, env->num_triggers);
for (i = 0; i < env->num_triggers; i++) {
--
2.43.0
