On Thu, Jul 2, 2026 at 11:58 PM Daniel Henrique Barboza <[email protected]> wrote: > > riscv_imsic.c is the only caller. Having it sitting in the TCG only > cpu_helper.c gets in the way of --disable-tcg for no good reason. > > Signed-off-by: Daniel Henrique Barboza <[email protected]> > Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > hw/intc/riscv_imsic.c | 11 +++++++++++ > target/riscv/cpu.h | 3 --- > target/riscv/tcg/cpu_helper.c | 10 ---------- > 3 files changed, 11 insertions(+), 13 deletions(-) > > diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c > index ebb55191c7..d6b46cdca2 100644 > --- a/hw/intc/riscv_imsic.c > +++ b/hw/intc/riscv_imsic.c > @@ -376,6 +376,17 @@ static void riscv_imsic_reset_enter(Object *obj, > ResetType type) > } > } > > +static void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, > + privilege_mode_t priv, > + aia_ireg_rmw_fn rmw_fn, > + void *rmw_fn_arg) > +{ > + if (priv <= PRV_M) { > + env->aia_ireg_rmw_cb[priv] = rmw_fn; > + env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg; > + } > +} > + > static void riscv_imsic_realize(DeviceState *dev, Error **errp) > { > RISCVIMSICState *imsic = RISCV_IMSIC(dev); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7a4d8abe07..c9dfa7daff 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -680,9 +680,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, > uint64_t mask, > void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); > void riscv_cpu_interrupt(CPURISCVState *env); > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > -void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv, > - aia_ireg_rmw_fn rmw_fn, > - void *rmw_fn_arg); > > RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); > #endif /* !CONFIG_USER_ONLY */ > diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c > index 71a96a20ef..07d9222652 100644 > --- a/target/riscv/tcg/cpu_helper.c > +++ b/target/riscv/tcg/cpu_helper.c > @@ -590,16 +590,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, > uint64_t mask, uint64_t value) > return old; > } > > -void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t priv, > - aia_ireg_rmw_fn rmw_fn, > - void *rmw_fn_arg) > -{ > - if (priv <= PRV_M) { > - env->aia_ireg_rmw_cb[priv] = rmw_fn; > - env->aia_ireg_rmw_cb_arg[priv] = rmw_fn_arg; > - } > -} > - > static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask, > bool virt) > { > -- > 2.43.0 > >
