On Tue, Jun 30, 2026 at 8:46 PM <[email protected]> wrote: > > From: Frank Chang <[email protected]> > > Now that Zicclsm is supported, let's enable it for the following > compatible CPUs: > > - Base 32 CPU (to be backward compatible) > - Base 64 CPU (to be backward compatible) > - XuanTie (T-Head) C908 > - Tenstorrent Ascalon > - Ventana Veyron V1 > - XiangShan Kunminghu > - MIPS P8700 (ISA doesn't include Zicclsm, but their datasheet claims that > it has unaligned load/store support in hardware) > > Signed-off-by: Frank Chang <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index bff3ed5de14..a3cccdfed3c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3021,6 +3021,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.ext_zicbom = true, > .cfg.ext_zicbop = true, > .cfg.ext_zicboz = true, > + .cfg.ext_zicclsm = true, > .cfg.ext_zicntr = true, > .cfg.ext_zicsr = true, > .cfg.ext_zifencei = true, > @@ -3093,6 +3094,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.ext_zicbom = true, > .cfg.ext_zicbop = true, > .cfg.ext_zicboz = true, > + .cfg.ext_zicclsm = true, > .cfg.ext_zicntr = true, > .cfg.ext_zicsr = true, > .cfg.ext_zifencei = true, > @@ -3179,6 +3181,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.ext_zbs = true, > .cfg.ext_zkt = true, > .cfg.ext_zbkc = true, > + .cfg.ext_zicclsm = true, > .cfg.ext_zicsr = true, > .cfg.ext_zifencei = true, > .cfg.ext_zihintpause = true, > @@ -3222,6 +3225,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.ext_zicbom = true, > .cfg.ext_zicbop = true, > .cfg.ext_zicboz = true, > + .cfg.ext_zicclsm = true, > .cfg.ext_zicntr = true, > .cfg.ext_zicond = true, > .cfg.ext_zicsr = true, > @@ -3270,6 +3274,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > > /* ISA extensions */ > .cfg.mmu = true, > + .cfg.ext_zicclsm = true, > .cfg.ext_zifencei = true, > .cfg.ext_zicsr = true, > .cfg.pmp = true, > @@ -3329,6 +3334,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > * The RISC-V Instruction Set Manual: Volume I > * Unprivileged Architecture > */ > + .cfg.ext_zicclsm = true, > .cfg.ext_zicntr = true, > .cfg.ext_zihpm = true, > .cfg.ext_zihintntl = true, > @@ -3385,6 +3391,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, > .priv_spec = PRIV_VERSION_1_12_0, > .cfg.max_satp_mode = VM_1_10_SV48, > + .cfg.ext_zicclsm = true, > .cfg.ext_zifencei = true, > .cfg.ext_zicsr = true, > .cfg.mmu = true, > -- > 2.43.0 > >
