Hi Bin, On 30/6/26 15:57, Bin Meng wrote:
This series fixes dummy-cycle accounting for SPI NOR fast-read operations across the m25p80 flash model and several SSI controller models. The root problem is that the affected code paths mixed two different units. Flash datasheets and controller registers often describe fast-read dummy phases in clock cycles, while the SSI bus interface used by these models transfers byte-sized words to the flash. As a result, some paths treated cycle counts as byte counts directly, and other paths compensated in controller-specific ways that duplicated flash command semantics.
The final patch documents the intended ownership boundary: flash models own command semantics and dummy-byte consumption, while controller models own hardware-generated dummy phases and cycle-to-byte conversion.
I'd blame the API. I'd feel safer having the block/ layer use bit cycles, and a core layer converting bits to bytes when calling the SSI layer. Maybe too late to improve. The documentation you added is helpful, but I'm pretty sure we'll introduce more regressions. Anyway, thanks for your work :)
Some background: While recently working on some device modeling, I hit this issue again. I then realized that I had sent a fix series for it more than five years ago, but it never made it upstream. This series picks up that old work, refreshes it against the current tree, and fixes several issues in the SPI controller models. The original series is available at [1]. I have tried to verify all the SPI controller changes by booting real-world guest software to ensure the change does not break anything. [1] https://lore.kernel.org/qemu-devel/[email protected]/
(Could we add this as a functional test?)
