On 7/7/26 08:35, Philippe Mathieu-Daudé wrote:
On 1/7/26 11:22, Daniel Henrique Barboza wrote:
We're hardcoding faulting type as READ, where it could very well be a
write access, and we're not recording the faulting addr/iova.
A note was added in the fault_type logic because I wasn't able to
trivially handle a probable code repeitition it in this same patch.
Something to do in a later date.
Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3564
Signed-off-by: Daniel Henrique Barboza <[email protected]>
---
hw/riscv/riscv-iommu.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
@@ -1339,6 +1340,7 @@ static RISCVIOMMUContext
*riscv_iommu_ctx(RISCVIOMMUState *s,
.process_id = process_id,
};
unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
+ uint32_t fault_type;
s/uint32_t/enum riscv_iommu_fq_ttypes/ (can be cleaned later).
(and if cleaning that, also riscv_iommu_report_fault() argument)
