On Wed, Jul 8, 2026 at 12:54 AM Corvin Köhne <[email protected]> wrote: > > From: Corvin Köhne <[email protected]> > > When adding a reset value for DDRIOB_DCI_CTRL in c8ba862dbfdc, we haven't > noticed that a reset value already exists. DDRIOB is a 32 bit register, so > incrementing it by 12 will access the DDRIOB_DCI_CTRL register. According to > the manual [1] the correct reset value is 0x00000020. Additionally, > c8ba862dbfdc won't work with a reset value of 0x00000021 because it tries to > detect a toggle of the reset bit (bit 0). Therefore, we drop the old reset > value and keep the new one introduced in c8ba862dbfdc. > > [1] > https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Register-slcr-DDRIOB_DCI_CTRL > > Fixes: c8ba862dbfdc ("hw/misc/zynq_slcr: Add logic for DCI configuration") > Signed-off-by: Corvin Köhne <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > hw/misc/zynq_slcr.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c > index 0ae5d607be9b..d0f899c3be4d 100644 > --- a/hw/misc/zynq_slcr.c > +++ b/hw/misc/zynq_slcr.c > @@ -427,7 +427,6 @@ static void zynq_slcr_reset_init(Object *obj, ResetType > type) > = s->regs[R_DDRIOB + 3] = 0x00000e00; > s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] > = 0x00000e00; > - s->regs[R_DDRIOB + 12] = 0x00000021; > > s->regs[R_DDRIOB_DCI_CTRL] = 0x00000020; > } > -- > 2.47.3 > >
