> -----Original Message----- > From: Eric Auger <[email protected]> > Sent: 07 July 2026 09:50 > To: [email protected]; [email protected]; qemu- > [email protected]; [email protected]; [email protected]; > [email protected]; Shameer Kolothum Thodi > <[email protected]>; Nicolin Chen <[email protected]>; Nathan > Chen <[email protected]>; [email protected] > Subject: [PATCH v3 1/5] hw/arm/smmuv3: Fix off-by-one bug in alignment > strtab mask > > External email: Use caution opening links or attachments > > > The stream table base address needs to be aligned to its size. > > With FMT == 0 (linear stream table), the table size is log2size * > STE_SIZE (2^6). So the spec says the base address > must have ADDR[LOG2SIZE + 5:0] = 0. > > With FMT == 1 (2 level stream table), the table size is > (log2size - split) * L1STD_SIZE (2^3) So the spec days > the effective base address is aligned by the SMMU to the larger of > 64 bytes or the first-level table size: > ADDR[MAX(5, (LOG2SIZE - SPLIT - 1 + 3)):0] = 0. > > MAKE_64BIT_MASK() second argument is a size and not a shift, so > fix this off-by-one computation. > > Subsequent patches will fix the risk of overflow in MAKE_64BIT_MASK() > > Signed-off-by: Eric Auger <[email protected]> Reviewed-by: Shameer Kolothum <[email protected]> Thanks, Shameer
