We don't need to check PPC_ISA207S, because that's already done starting with register_book3s_207_dbg_sprs(). Replace target_ulong with uint64_t, as we're under TARGET_PPC64.
Signed-off-by: Richard Henderson <[email protected]> --- target/ppc/tcg-excp_helper.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 56ca66e7b5..99ffe4a820 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -330,23 +330,19 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) { #if defined(TARGET_PPC64) CPUPPCState *env = cpu_env(cs); + uint64_t priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); - if (env->insns_flags2 & PPC2_ISA207S) { - target_ulong priv; - - priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); - switch (priv) { - case 0x1: /* problem */ - return env->msr & ((target_ulong)1 << MSR_PR); - case 0x2: /* supervisor */ - return (!(env->msr & ((target_ulong)1 << MSR_PR)) && - !(env->msr & ((target_ulong)1 << MSR_HV))); - case 0x3: /* hypervisor */ - return (!(env->msr & ((target_ulong)1 << MSR_PR)) && - (env->msr & ((target_ulong)1 << MSR_HV))); - default: - g_assert_not_reached(); - } + switch (priv) { + case 0x1: /* problem */ + return env->msr & (1ull << MSR_PR); + case 0x2: /* supervisor */ + return (!(env->msr & (1ull << MSR_PR)) && + !(env->msr & (1ull << MSR_HV))); + case 0x3: /* hypervisor */ + return (!(env->msr & (1ull << MSR_PR)) && + (env->msr & (1ull << MSR_HV))); + default: + g_assert_not_reached(); } #endif -- 2.43.0
