Add the argument and ignore it so far in all targets.
Signed-off-by: Richard Henderson <[email protected]>
---
include/accel/tcg/cpu-ops.h | 2 +-
target/arm/internals.h | 2 +-
target/ppc/internal.h | 2 +-
target/riscv/debug.h | 2 +-
target/xtensa/cpu.h | 2 +-
accel/tcg/cpu-exec.c | 2 +-
target/arm/tcg/debug.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/ppc/tcg-excp_helper.c | 2 +-
target/riscv/debug.c | 2 +-
target/xtensa/dbg_helper.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index 568d82cdd3..3988bef520 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -264,7 +264,7 @@ struct TCGCPUOps {
* @debug_check_breakpoint: return true if the architectural
* breakpoint whose PC has matched should really fire.
*/
- bool (*debug_check_breakpoint)(CPUState *cpu);
+ bool (*debug_check_breakpoint)(CPUState *cpu, CPUBreakpoint *bp);
/**
* @io_recompile_replay_branch: Callback for cpu_io_recompile.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 4026f67579..49ec97bd1c 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -689,7 +689,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n);
void hw_breakpoint_update_all(ARMCPU *cpu);
/* Callback function for checking if a breakpoint should trigger. */
-bool arm_debug_check_breakpoint(CPUState *cs);
+bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp);
/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index a3bb12afd9..ec057afa92 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -304,7 +304,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
void ppc_cpu_debug_excp_handler(CPUState *cs);
-bool ppc_cpu_debug_check_breakpoint(CPUState *cs);
+bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp);
bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *reason);
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index a25d099b37..8eb9eccd4c 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -144,7 +144,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index,
target_ulong val);
target_ulong tinfo_csr_read(CPURISCVState *env);
void riscv_cpu_debug_excp_handler(CPUState *cs);
-bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
void riscv_trigger_realize(CPURISCVState *env);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index ab42b4be00..590371c4dc 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -591,7 +591,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
-bool xtensa_debug_check_breakpoint(CPUState *cs);
+bool xtensa_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp);
#endif
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
void xtensa_count_regs(const XtensaConfig *config,
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 257211235d..6547cc70c9 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -328,7 +328,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, vaddr
pc,
#else
const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
assert(tcg_ops->debug_check_breakpoint);
- match_bp = tcg_ops->debug_check_breakpoint(cpu);
+ match_bp = tcg_ops->debug_check_breakpoint(cpu, bp);
#endif
}
diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c
index 50b90ad675..306106b7e8 100644
--- a/target/arm/tcg/debug.c
+++ b/target/arm/tcg/debug.c
@@ -351,7 +351,7 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
return true;
}
-bool arm_debug_check_breakpoint(CPUState *cs)
+bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 6f5dc06b3b..86832cfdf2 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -132,7 +132,7 @@ static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
}
#ifndef CONFIG_USER_ONLY
-static bool x86_debug_check_breakpoint(CPUState *cs)
+static bool x86_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index b04f07a637..eb78a6a104 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -331,7 +331,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs)
#endif
}
-bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
+bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp)
{
#if defined(TARGET_PPC64)
CPUPPCState *env = cpu_env(cs);
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 1b88cd136c..5c378dd2e8 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -941,7 +941,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
}
}
-bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *ignore)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
index 20ddc527f8..557a7852c8 100644
--- a/target/xtensa/dbg_helper.c
+++ b/target/xtensa/dbg_helper.c
@@ -64,7 +64,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i,
uint32_t v)
env->sregs[IBREAKA + i] = v;
}
-bool xtensa_debug_check_breakpoint(CPUState *cs)
+bool xtensa_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp)
{
CPUXtensaState *env = cpu_env(cs);
unsigned int i;
--
2.43.0
