+ Harsh
On 7/11/26 00:07, Philippe Mathieu-Daudé wrote:
Hi,
(committed as d5ee641cfc5c3cbd51282d0c6e996f990b9d62a3)
On 4/9/23 11:06, Cédric Le Goater wrote:
From: Nicholas Piggin <[email protected]>
ISA v2.07S introduced the watchpoint facility based on the DAWR0
and DAWRX0 SPRs. Implement this in TCG.
Signed-off-by: Nicholas Piggin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
---
target/ppc/cpu.h | 4 +++
target/ppc/helper.h | 2 ++
target/ppc/internal.h | 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu.c | 59 ++++++++++++++++++++++++++++++++++++++++
target/ppc/cpu_init.c | 6 ++--
target/ppc/excp_helper.c | 52 ++++++++++++++++++++++++++++++++++-
target/ppc/machine.c | 1 +
target/ppc/misc_helper.c | 10 +++++++
target/ppc/translate.c | 13 +++++++++
10 files changed, 147 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index d9c665ce1819..62e1c15e3d33 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -128,6 +128,65 @@ void ppc_store_ciabr(CPUPPCState *env, target_ulong val)
env->spr[SPR_CIABR] = val;
ppc_update_ciabr(env);
}
+
+void ppc_update_daw0(CPUPPCState *env)
dawr0
+{
+ CPUState *cs = env_cpu(env);
+ target_ulong deaw = env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60);
+ uint32_t dawrx = env->spr[SPR_DAWRX0];
+ int mrd = extract32(dawrx, PPC_BIT_NR(48), 54 - 48);
+ bool dw = extract32(dawrx, PPC_BIT_NR(57), 1);
+ bool dr = extract32(dawrx, PPC_BIT_NR(58), 1);
+ bool hv = extract32(dawrx, PPC_BIT_NR(61), 1);
+ bool sv = extract32(dawrx, PPC_BIT_NR(62), 1);
+ bool pr = extract32(dawrx, PPC_BIT_NR(62), 1);
Is it deliberate @sv and @pr are the same?
I think it's a typo. Should be 63. Harsh could you confirm please ?
Thanks,
C.
