On 7/10/26 05:54, [email protected] wrote:
From: Alistair Francis <[email protected]>
RISC-V PR for 11.1
* Fix IOMMU fault type for spa_fetch() faults
* Check IOMMU for reserved PTE bits
* Fault when IOMMU !PTE_U and no priv access
* Fault IOMMU for non-user PTE in G_STAGE
* Check IOMMU reserved MSI PTE basic bits
* Record fault on IOMMU-generated MSI write
* Move RISC-V TCG files and fix --disable-tcg
* Check for misaligned IOMMU IOHGATP_PPN
* Update IOMMU ioval2 when faulting in spa_fetch()
* Forbid IOMMU GATE/SADE if caps.AMO_HWADD is zero
* Set IOMMU ftype and iova in riscv_iommu_ctx()
* Check PCIe DOE mailbox length for overflows
* Add extensions after v7.1-rc4 update
* Remove job building OpenSBI firmware binaries
* Correct ACPI field sequence in SPCR table
Is it the same as usual for riscv pull requests, -- everything with
Fixes: or Resolves: tag should be picked up for the current qemu stable
releases?
(Cc'ing Daniel too since he has largest share of contributions here).
Thanks,
/mjt
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Alistair Francis (1):
hw/pci/pcie_doe: Check mailbox length for overflows
Bin Meng (1):
gitlab-ci: Remove job building OpenSBI firmware binaries
Daniel Henrique Barboza (32):
hw/riscv/riscv-iommu.c: fix fault type for spa_fetch() faults
hw/riscv/riscv-iommu.c: check for reserved PTE bits
hw/riscv/riscv-iommu.c: fault when !PTE_U and no priv access
hw/riscv/riscv-iommu.c: fault for non-user PTE in G_STAGE
hw/riscv/riscv-iommu.c: check reserved MSI PTE basic bits
hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write
target/riscv: move valid_vm_* satp arrays to cpu.c
hw/riscv, target/riscv: move pmu fdt function to fdt-common.c
target/riscv: move TCG only files to tcg subdir
target/riscv/machine.c: do not migrate pmp state with kvm
target/riscv: move pmp files to tcg subdir
target/riscv: tidy up riscv_sysemu_ops
target/riscv: move debug.h to tcg subdir
target/riscv: remove csr.h from kvm-cpu.c
target/riscv: move csr.h to tcg subdir
target/riscv: move custom_csrs logic to tcg-cpu.c
target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
target/riscv: move some irq helpers to cpu.c
target/riscv: move riscv_cpu_claim_interrupts to cpu.c
target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state
target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
hw/riscv/riscv_hart.c isolate tcg only bits
target/riscv/gdbstub.c: isolate TCG only checks
target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
target/riscv/tcg: remove unused riscv_cpu_get_geilen()
target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN
hw/riscv/riscv-iommu.c: update ioval2 when faulting in spa_fetch()
hw/riscv/riscv-iommu: forbid GATE/SADE if caps.AMO_HWADD is zero
hw/riscv/riscv-iommu.c: set ftype and iova in riscv_iommu_ctx()
Heinrich Schuchardt (3):
tests: allow differences in SPCR
hw/acpi: correct field sequence in SPCR table
tests: update SPCR loongarch64 and riscv64 test data
Wang Yechao (1):
target/riscv/kvm: add extensions after v7.1-rc4 update
Zephyr Li (2):
target/riscv: Remove unused tcg/tcg.h include
gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
