From: Daniel Henrique Barboza <[email protected]>
riscv-iommu spec: "If SADE is 1, the IOMMU updates A and D bits in
first-stage PTEs atomically. If SADE is 0, the IOMMU causes a
page-fault corresponding to the original access type if the
A bit is 0 or if the memory access is a store and the D bit is 0.".
Note that SADE=0 and A=0 will always cause a fault regardless of the
original access type. Right now we're faulting in this case just for
reads.
Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3551
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
(cherry picked from commit 64ce9ac18757d79f3b5b337f7bcbdd0dabef3ce1)
Signed-off-by: Michael Tokarev <[email protected]>
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 917a9690810..b2e2ee486e9 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -470,7 +470,7 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s,
RISCVIOMMUContext *ctx,
break; /* Read access check failed */
} else if ((iotlb->perm & IOMMU_WO) && !(pte & PTE_W)) {
break; /* Write access check failed */
- } else if ((iotlb->perm & IOMMU_RO) && !ade && !(pte & PTE_A)) {
+ } else if (!ade && !(pte & PTE_A)) {
break; /* Access bit not set */
} else if ((iotlb->perm & IOMMU_WO) && !ade && !(pte & PTE_D)) {
break; /* Dirty bit not set */
--
2.47.3
