From: Randy Schifflin <[email protected]> Fixes TCG generation for sh4 `fipr` and `ftrv` instructions. Updates the current logic for these instructions to check the FPSCR register appropriately (according to the sh4 cpu manual, `fipr` and `ftrv` are only defined when the FPSCR register PR flag is 0). Also fixes the mth/nth-vector operands by multiplying by 4 to convert to the correct floating point register offset.
Signed-off-by: Randy Schifflin <[email protected]> Reviewed-by: Yoshinori Sato <[email protected]> Message-ID: <20260629-fixup-sh4-tcg-fpu-instructions-b4-v1-2-4356b305f...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> (cherry picked from commit 614a52cf549e6aefa656634b4d3fa0d4686125c6) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index d70587f328d..bc3b7c44dde 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -485,7 +485,7 @@ void helper_ftrv(CPUSH4State *env, uint32_t n) float32 p; bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16; - bank_vector = (env->sr & FPSCR_FR) ? 16 : 0; + bank_vector = (env->sr & FPSCR_FR) ? 16 + n : n; set_float_exception_flags(0, &env->fp_status); for (i = 0 ; i < 4 ; i++) { r[i] = float32_zero; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index bcdd5588183..6286862241e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -377,11 +377,6 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) goto do_illegal; \ } -#define CHECK_FPSCR_PR_1 \ - if (!(ctx->tbflags & FPSCR_PR)) { \ - goto do_illegal; \ - } - #define CHECK_SH4A \ if (!(ctx->features & SH_FEATURE_SH4A)) { \ goto do_illegal; \ @@ -1746,22 +1741,22 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf0ed: /* fipr FVm,FVn */ CHECK_FPU_ENABLED - CHECK_FPSCR_PR_1 + CHECK_FPSCR_PR_0 { - TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3); - TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); + TCGv m = tcg_constant_i32(((ctx->opcode >> 8) & 3) << 2); + TCGv n = tcg_constant_i32(((ctx->opcode >> 10) & 3) << 2); gen_helper_fipr(tcg_env, m, n); return; } break; case 0xf0fd: /* ftrv XMTRX,FVn */ CHECK_FPU_ENABLED - CHECK_FPSCR_PR_1 + CHECK_FPSCR_PR_0 { if ((ctx->opcode & 0x0300) != 0x0100) { goto do_illegal; } - TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); + TCGv n = tcg_constant_i32(((ctx->opcode >> 10) & 3) << 2); gen_helper_ftrv(tcg_env, n); return; } -- 2.47.3
