Hi Max
On Sat, Jul 14, 2012 at 9:49 PM, Max Filippov <[email protected]> wrote:
>>> I don't think so, please check for example target-ppc/translate.c:4192
>>> on how supervisor only mfsr is handled there.
>>>
>>
>> Thank you for comment, Blue.
>>
>> is this code OK?
>
> Shouldn't there also be an exception in softmmu mode
> if the CPU is not in supervisor mode?
>
Sorry, I...
May you give me more comment? I'm not sure about this.
>>
>> case 0x2d: /* l.mfspr */
>> LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
>> {
>> #if defined(CONFIG_USER_ONLY)
>> gen_illegal_exception(dc);
>> #else
>> TCGv_i32 ti = tcg_const_i32(I16);
>> gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti);
>> tcg_temp_free_i32(ti);
>> #endif
>> }
>> break;
>>
>> case 0x30: /* l.mtspr */
>> LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11);
>> {
>> #if defined(CONFIG_USER_ONLY)
>> gen_illegal_exception(dc);
>> #else
>> TCGv_i32 im = tcg_const_i32(tmp);
>> gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im);
>> tcg_temp_free_i32(im);
>> #endif
>> }
>> break;
>>
>
> --
> Thanks.
> -- Max
Regards,
Jia.
