Hi Alistair and Chao, Thank you both very much for the reviews and references.
I will split v2 into three patches: one adding the IOMUX device model, one wiring it into the K230 SoC, and one adding the qtest coverage. I will also remove the explicit offset, size, and alignment checks from the read and write callbacks, since the MemoryRegion size and MemoryRegionOps access constraints already enforce the valid MMIO range and aligned 32-bit accesses. For the currently modeled and tested use cases, the device only needs register-backed storage. The SDK U-Boot pinctrl-single driver and the SDK Linux IOMUX-related code paths I checked use 32-bit read-modify-write accesses and require the configuration values to be retained. On real hardware, writing these registers changes the pin function and electrical configuration. However, the current K230 machine does not model physical pin routing or electrical characteristics, and I have not found any additional register side effects required by the U-Boot or Linux code paths I tested. I will update v2 to follow the documented bit-level access permissions: bit 31 (DI) is read-only, bits 30 through 14 are read-only reserved bits, and bits 13 through 0 are read-write configuration fields. Guest writes will use a 0x00003fff writable mask, so they cannot modify bit 31 or the reserved bits. I will also add qtests covering writable fields, read-only fields, reserved bits, and normal read-modify-write accesses. The SoC memory map reserves a 0x800-byte window for the Main IOMUX, but the documentation defines only 64 pin registers at offsets 0x00 through 0xfc. I will model only these documented registers in v2 and leave offsets 0x100 through 0x7ff reserved/unimplemented. I will include these changes in v2. Thanks, Kangjie
