Octeon firmware performs unaligned memory accesses during early DDR setup. Use QEMU's unaligned memory operation mode for Octeon translations, matching the existing treatment for MIPS R6 and Loongson3A.
Signed-off-by: Kirill A. Korinsky <[email protected]> --- target/mips/tcg/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 123ba6aecd..d83f76e514 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15193,6 +15193,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #endif ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && (ctx->insn_flags & (ISA_MIPS_R6 | + INSN_OCTEON | INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN; if (tb_flags & TB_FLAG_MIPS_FIXADE) { ctx->default_tcg_memop_mask = MO_UNALN; -- 2.54.0
