From: Eric Auger <[email protected]> Spec says: Bits L2Ptr[N:0] are treated as 0 by the SMMU, where N == 5 + (Span - 1).
Let's enforce this alignment. Signed-off-by: Eric Auger <[email protected]> Reviewed-by: Shameer Kolothum <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]> --- hw/arm/smmuv3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 9008ba7acd9..ed19536a4dc 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -728,6 +728,8 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) max_l2_ste = (1 << span) - 1; l2ptr = l1std_l2ptr(&l1std); + + l2ptr &= ~MAKE_64BIT_MASK(0, 6 + (span - 1)); trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset, l2ptr, l2_ste_offset, max_l2_ste); if (l2_ste_offset > max_l2_ste) { -- 2.43.0
