[PATCH 2/2] target/arm: GICv5 cpuif: Writes to ICC_APR_EL1 can change IRQ/FIQ

[Peter Maydell]

The ICC_APR_EL1 register values change the current running priority,
which we use in our calculations in gic_hppi().  Changing them can
affect whether we have a HPPI, and so the value of the IRQ/FIQ
outputs.  We need to trigger an update in the register writefn.

Fixes: 9bd90bddb79 ("target/arm: GICv5 cpuif: Signal IRQ or FIQ")
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
 target/arm/tcg/gicv5-cpuif.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index 8e2a08fdb6f..a6e6c440849 100644
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -495,6 +495,7 @@ static void gic_icc_apr_el1_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
     GICv5Domain domain = gicv5_logical_domain(env);
     value &= 0xffffffff;
     env->gicv5_cpuif.icc_apr[domain] = value;
+    gicv5_update_irq_fiq(env);
 }
 
 static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
-- 
2.43.0