Hi,
On 14/7/26 05:40, Yanfeng Liu wrote:
Alistair,
I was using 0x10000100 at first but soon noticed it is in the same MMU
page as UART0, which is difficult for pass-through hypervisor guests.
So current approach seems a little more flexible?
(please do not top-post on technical mailing lists)
It would have be clearer if you precised that ...
Regards,
yanfeng
On Tue, 2026-07-14 at 01:13 +0000, Alistair Francis wrote:
On Fri, 2026-07-03 at 12:24 +0800, Yanfeng Liu wrote:
This adds optional UART1 to RiscV virt board if required at
runtime to simplify multicore development.
Note that UART0 remains default serial_hd(0) and it is:
- the lowest address UART
- first serial in DTB
- behind /aliases/serial0 in DTB
- the /chosen/stdout-path in DTB
... here [*] ...
Signed-off-by: Yanfeng Liu <[email protected]>
---
docs/system/riscv/virt.rst | 5 ++++-
hw/riscv/virt-acpi-build.c | 12 ++++++++----
hw/riscv/virt.c | 39 ++++++++++++++++++++++++++++------
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 33775a61fd..9a112ccdef 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
... and added a hint comment about alignment here.
@@ -96,6 +96,7 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX)
},
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
+ [VIRT_UART1] = { 0x1000a000, 0x100 },
This could be at address 0x10000100 instead and squish up against
UART0.
Otherwise:
Reviewed-by: Alistair Francis <[email protected]>
Alistair
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
