We announce the availability of OpenVADL 0.3.0 (https://github.com/OpenVADL/openvadl).
OpenVADL now supports the specification of tensor instructions with preliminary auto vectorization to generate QEMU TCG vector instructions. Furthermore, dynamically bi-endian memory access and aliasing of the program counter with the general purpose register file is supported (needed for the specification of AArch32). A hardware generator for scalar processor pipelines is working now too. The slides from the FSiC conference give some details regarding the implementation and preliminary performance numbers: https://wiki.f-si.org/images/6/69/OpenVADLfsic2026.pdf Andreas -- [email protected] <mailto:[email protected]> Andreas Krall www.complang.tuwien.ac.at/andi <http://www.complang.tuwien.ac.at/andi> Compilers and Languages, TU Wien tel: (+431) 58801/18511 Argentinierstr. 8/4/194-5 fax: (+431) 58801/18598 A-1040 Wien AUSTRIA EUROPE
