Add a CN73xx CPU definition for the Octeon III machine. The PRId, FPU
FIR, and L2 cache geometry come from EdgeRouter Infinity ER-8-XG data;
the remaining CP0 fields come from a Juniper SRX300 CN70xx/CN71xx dump.
---
target/mips/cpu-defs.c.inc | 42 ++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index cc1916232f..ee638568db 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -1023,6 +1023,48 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /*
+ * Minimal Octeon CN73xx model for EBB7304 firmware. PRId, FPU FIR,
+ * and L2 cache geometry match a Ubiquiti EdgeRouter Infinity
+ * ER-8-XG; the remaining CP0 values are a placeholder Octeon III
+ * model derived from a Juniper SRX300 CN70xx/CN71xx dump.
+ */
+ .name = "OcteonCN73XX",
+ .CP0_PRid = 0x000D9702,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) |
+ (0x3F << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (6 << CP0C1_IL) | (7 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (0 << CP0C1_DL) | (7 << CP0C1_DA) |
+ (1 << CP0C1_C2) | (1 << CP0C1_PC) |
+ (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (6 << CP0C2_SL) |
+ (15 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) |
+ (1 << CP0C3_VZ) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
+ (0x3c << CP0C4_KScrExist),
+ .CP0_Config7 = 1 << CP0C7_WII,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .SYNCI_Step = 32,
+ .CCRes = 1,
+ .CP0_Status_rw_bitmask = 0x36F8FFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x97 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 49,
+ .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#endif
};
--
2.54.0
