On 7/16/26 05:35, Daniel Henrique Barboza wrote:
From: Nicholas Piggin <[email protected]>When an mc/mc6 trigger triggers on a load/store and raises a breakpoint exception, put the matching memory address into tval, as is already done for exec addresses matching. Tval for breakpoint exceptions is optional in the spec, but it seems more consistent to implement it for load/store if exec is implemented. Fixes: a42bd00166 ("target/riscv: debug: Determine the trigger type from tdata1.type") Signed-off-by: Nicholas Piggin <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/tcg/debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index f671ae67f8..7ecbe01fb2 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -1077,6 +1077,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)if ((wp->flags & flags) && (wp->vaddr == addr)) {if (do_trigger_action(env, i)) { + env->badaddr = wp->vaddr; return true; } } @@ -1095,6 +1096,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)if ((wp->flags & flags) && (wp->vaddr == addr)) {if (do_trigger_action(env, i)) { + env->badaddr = wp->vaddr; return true; } }
check_watchpoint shouldn't set badaddr; the subsequent call to debug_excp_handler should. Same vs patch 10 and breakpoints. Also, wp->hitaddr is the address that actually triggered within [vaddr, vaddr+len). r~
