On 18/7/26 04:16, Yanfeng Liu wrote:
This adds optional UART1 to RiscV virt board if required at
runtime to simplify multicore development.
Note that UART0 remains default serial_hd(0) and it is:
- the lowest address UART
- first serial in DTB
- behind /aliases/serial0 in DTB
- the /chosen/stdout-path in DTB
Note that UART1 is placed at different page from UART0 to
support page level isolation.
Signed-off-by: Yanfeng Liu <[email protected]>
---
docs/system/riscv/virt.rst | 5 ++++-
hw/riscv/virt-acpi-build.c | 12 ++++++++----
hw/riscv/virt.c | 40 ++++++++++++++++++++++++++++----------
include/hw/riscv/virt.h | 3 +++
4 files changed, 45 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
