Hi, Just a gentle ping on this series.
This series fixes several Hygon Dhyana vendor-specific CPU behavior gaps where QEMU currently keys AMD-compatible paths only on AuthenticAMD.
The guest-visible changes are gated by x-hygon-vendor-abi-fixes and kept off for pc-11.0 and older machine types. The KVM runtime changes do not change guest CPU model ABI.
Any comments would be appreciated. Thanks, Tina On 7/6/2026 1:55 PM, [email protected] wrote:
From: Tina Zhang <[email protected]> Hygon Dhyana uses the HygonGenuine vendor string, but a number of guest-visible and KVM-facing interfaces follow AMD-compatible behavior. QEMU currently keys several of these paths only on AuthenticAMD, so Hygon guests can see vendor-inconsistent CPUID/MSR state or use the wrong KVM PMU/MCE handling paths. This series makes those checks explicit for Hygon where appropriate. Guest-visible CPU ABI changes are gated by the new x-hygon-vendor-abi-fixes property. The property defaults to true for new machine types and is disabled for pc-11.0 and older, so existing machine types keep their previous Hygon ABI for migration compatibility. The KVM injected-MCE and PMU path changes are not CPUID model table changes. They make QEMU use the AMD-compatible runtime handling that Linux/KVM already uses for Hygon. The series covers: * AMD CPUID[0x80000001].EDX aliases for Hygon * hiding Intel cache CPUID leaves 2 and 4 for Hygon * hiding IA32_ARCH_CAPABILITIES for Hygon unless old ABI requires it * AMD MCE status encoding for Hygon memory-failure injection * AMD PMU MSR setup/save/restore paths for Hygon * disabling Intel-style MCA broadcast for Hygon injected MCEs * AMD IOMMU HT GPA hole layout for Hygon on new machine types * AMD legacy cache fallback for Hygon when legacy-cache=on * AMD-shaped default ucode-rev value for Hygon Tests were added for the Dhyana CPUID/ucode compatibility behavior and for the Hygon HT GPA hole memory-layout case. Tested with: ninja -C build build/pyvenv/bin/meson test -C build --print-errorlogs \ qemu:qtest-i386/test-x86-cpuid-compat \ qemu:qtest-x86_64/test-x86-cpuid-compat \ qemu:func-x86_64-mem_addr_space Tina Zhang (9): target/i386: Sync AMD CPUID aliases for Hygon target/i386: Hide Intel cache CPUID leaves for Hygon target/i386: Hide ARCH_CAPABILITIES for Hygon target/i386/kvm: Use AMD MCE status encoding for Hygon target/i386/kvm: Use AMD PMU MSR paths for Hygon target/i386: Do not broadcast injected MCEs for Hygon hw/i386: Apply AMD IOMMU HT GPA hole to Hygon target/i386: Use AMD legacy cache fallback for Hygon target/i386: Use AMD ucode-rev default for Hygon hw/i386/pc.c | 22 +++-- target/i386/cpu.c | 86 +++++++++++++---- target/i386/cpu.h | 12 +++ target/i386/helper.c | 6 +- target/i386/kvm/kvm.c | 36 +++++-- .../functional/x86_64/test_mem_addr_space.py | 36 +++++++ tests/qtest/test-x86-cpuid-compat.c | 95 +++++++++++++++++++ 7 files changed, 263 insertions(+), 30 deletions(-)
