From: Jay Chang <[email protected]> The Marvell 88E1111 PHY register 17 (PHY Specific Status Register) bit 10 reports real-time link status. Previously, this register returned a fixed value of 0x8800 with bit 10 always cleared, causing U-Boot to always detect "No link" even when the link was up.
Signed-off-by: Jay Chang <[email protected]> Reviewed-by: Frank Chang <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Peter Maydell <[email protected]> (cherry picked from commit 83927347227c91dd659e7ed718d656ed0d551ab6) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 457952af196..d2f98db1026 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -103,6 +103,9 @@ static unsigned int tdk_read(struct PHY *phy, unsigned int req) case 17: /* Marvell PHY on many xilinx boards. */ r = 0x8000; /* 1000Mb */ + if (phy->link) { + r |= 0x0400; /* Link is up */ + } break; case 18: { -- 2.47.3
