On 7/14/2026 3:01 AM, Flavien Solt wrote:
The AIA specification requires an IOMMU to send the configured notice MSI after
storing an MSI to an MRIF even when the corresponding interrupt-enable bit is
clear. The problem is that riscv_iommu_msi_write() currently reads the MRIF
interrupt-enable doubleword and suppresses the notice MSI when the bit is zero.
This patch removes the enable-word read and always sends the notice MSI after
updating the MRIF pending bit.
Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Cc: [email protected]
Signed-off-by: Flavien Solt <[email protected]>
---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Tested with a deterministic qtest using qemu-system-riscv64.
After this patch we get:
enable=0: pending=0x20 notice=0x12d
enable=1: pending=0x20 notice=0x12d
hw/riscv/riscv-iommu.c | 15 +--------------
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index f6865d1..9627cab 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -788,20 +788,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState
*s,
goto err;
}
- /* Get MRIF enable bits */
- addr = addr + sizeof(intn);
- res = dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs);
- if (res != MEMTX_OK) {
- cause = RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT;
- goto err;
- }
-
- if (!(intn & data)) {
- /* notification disabled, MRIF update completed. */
- return MEMTX_OK;
- }
-
- /* Send notification message */
addr = PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN));
n190 = get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) |
(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID_MSB) << 10);
base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
--
2.54.0
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