[PATCH 22/27] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE

[Pierrick Bouvier]

Signed-off-by: Pierrick Bouvier <pierrick.bouv...@oss.qualcomm.com>
---
 hw/core/null-machine.c          | 5 +----
 hw/riscv/virt.c                 | 2 --
 include/hw/riscv/machines-qom.h | 6 ------
 target-info-qom.c               | 8 --------
 target/riscv/machine.c          | 4 ----
 5 files changed, 1 insertion(+), 24 deletions(-)

diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 2aa748233b3..2f008c4a702 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -56,7 +56,4 @@ static void machine_none_machine_init(MachineClass *mc)
     mc->no_cdrom = 1;
 }
 
-DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
-                               { TYPE_TARGET_RISCV32_MACHINE },
-                               { TYPE_TARGET_RISCV64_MACHINE },
-                               { })
+DEFINE_MACHINE("none", machine_none_machine_init)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 51bac47a91d..f9de8827624 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1791,8 +1791,6 @@ static const TypeInfo virt_machine_typeinfo = {
     .instance_size = sizeof(RISCVVirtState),
     .interfaces = (const InterfaceInfo[]) {
          { TYPE_HOTPLUG_HANDLER },
-         { TYPE_TARGET_RISCV32_MACHINE },
-         { TYPE_TARGET_RISCV64_MACHINE },
          { }
     },
 };
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 5a5b5e05f58..0f9f3b94eac 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -13,12 +13,6 @@
 #include "qemu/target-info.h"
 #include "qemu/target-info-qom.h"
 
-#define TYPE_TARGET_RISCV32_MACHINE \
-        "target-info-riscv32-machine"
-
-#define TYPE_TARGET_RISCV64_MACHINE \
-        "target-info-riscv64-machine"
-
 /*
  * Interfaces specifying whether a given QOM object is available in
  * qemu-system-riscv32, qemu-system-riscv64, or both.
diff --git a/target-info-qom.c b/target-info-qom.c
index 30982d9d18b..5e0f21a319c 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -26,14 +26,6 @@ static const TypeInfo target_info_types[] = {
         .parent         = TYPE_INTERFACE,
         .class_size     = sizeof(TargetSpecificClass),
     },
-    {
-        .name           = TYPE_TARGET_RISCV32_MACHINE,
-        .parent         = TYPE_INTERFACE,
-    },
-    {
-        .name           = TYPE_TARGET_RISCV64_MACHINE,
-        .parent         = TYPE_INTERFACE,
-    },
 };
 
 DEFINE_TYPES(target_info_types)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 507e862f061..484a3730ef4 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -539,18 +539,14 @@ const VMStateDescription vmstate_riscv_cpu = {
 
 const InterfaceInfo riscv32_machine_interfaces[] = {
     { TYPE_TARGET_SPECIFIC },
-    { TYPE_TARGET_RISCV32_MACHINE },
     { }
 };
 
 const InterfaceInfo riscv64_machine_interfaces[] = {
     { TYPE_TARGET_SPECIFIC },
-    { TYPE_TARGET_RISCV64_MACHINE },
     { }
 };
 
 const InterfaceInfo riscv32_64_machine_interfaces[] = {
-    { TYPE_TARGET_RISCV32_MACHINE },
-    { TYPE_TARGET_RISCV64_MACHINE },
     { }
 };
-- 
2.43.0