The MMIO read-only and write-1-to-clear masks used by amdvi_init() are currently hardcoded. The hardcoded values look ambiguous.
Define named masks for the AMD-Vi MMIO registers to make the code easier to read and understand. Use status bit names that match the Linux AMD IOMMU driver definitions. This is a cleanup. Suggested-by: Sairaj Kodilkar <[email protected]> Signed-off-by: Dongli Zhang <[email protected]> --- hw/i386/amd_iommu.c | 5 +++-- hw/i386/amd_iommu.h | 24 ++++++++++++++++++++---- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2fd680c4ff..7ca6d33abb 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -2563,8 +2563,9 @@ static void amdvi_init(AMDVIState *s) memset(s->mmior, 0, AMDVI_MMIO_SIZE); amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES, amdvi_extended_feature_register(s), - 0xffffffffffffffef, 0); - amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, 0x98, 0x67); + AMDVI_MMIO_EXT_FEATURE_RO_MASK, 0); + amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, AMDVI_MMIO_STATUS_RO_MASK, + AMDVI_MMIO_STATUS_W1C_MASK); } static void amdvi_pci_realize(PCIDevice *pdev, Error **errp) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 687691ec1c..f86e37fe93 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -107,11 +107,25 @@ #define AMDVI_MMIO_CONTROL_INTCAPXTEN (1ULL << 51) /* MMIO status register bits */ -#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) -#define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) -#define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) -#define AMDVI_MMIO_STATUS_EVENT_INT (1 << 1) #define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0) +#define AMDVI_MMIO_STATUS_EVENT_INT (1 << 1) +#define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) +#define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) +#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) +#define AMDVI_MMIO_STATUS_PPR_OVF (1 << 5) +#define AMDVI_MMIO_STATUS_PPR_INT (1 << 6) +#define AMDVI_MMIO_STATUS_PPR_RUN (1 << 7) +#define AMDVI_MMIO_STATUS_GALOG_RUN (1 << 8) +#define AMDVI_MMIO_STATUS_GALOG_OVF (1 << 9) +#define AMDVI_MMIO_STATUS_GALOG_INT (1 << 10) + +#define AMDVI_MMIO_STATUS_RO_MASK \ + (AMDVI_MMIO_STATUS_EVT_RUN | AMDVI_MMIO_STATUS_CMDBUF_RUN | \ + AMDVI_MMIO_STATUS_PPR_RUN) +#define AMDVI_MMIO_STATUS_W1C_MASK \ + (AMDVI_MMIO_STATUS_EVT_OVF | AMDVI_MMIO_STATUS_EVENT_INT | \ + AMDVI_MMIO_STATUS_COMP_INT | AMDVI_MMIO_STATUS_PPR_OVF | \ + AMDVI_MMIO_STATUS_PPR_INT) #define AMDVI_CMDBUF_ID_BYTE 0x07 #define AMDVI_CMDBUF_ID_RSHIFT 4 @@ -227,6 +241,8 @@ AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) +#define AMDVI_MMIO_EXT_FEATURE_RO_MASK 0xffffffffffffffefULL + /* capabilities header */ #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ -- 2.39.3
