On Thu, Jul 23, 2026 at 11:18:28PM +0800, Bin Meng wrote:
> PolarFire SoC has a 2MiB L2 cache, so the maximum mapped size of
> L2LIM should be set to 2MiB too.
>
> Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
Thanks,
Chao
> ---
>
> hw/riscv/microchip_pfsoc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4017129c83..218cccab69 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -96,7 +96,7 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
> [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
> [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
> [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
> - [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
> + [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x200000 },
> [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
> [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
> [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
> --
> 2.34.1
>
