From: Frédéric Pétrot <[email protected]> The sstatus register assignment was performed before the write mask was fully constructed, leading to an incomplete update of sstatus fields on the experimental rv128 target.
Move the sstatus write after the mask completion so the full write mask is applied correctly. Signed-off-by: Frédéric Pétrot <[email protected]> --- target/riscv/tcg/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 36f2004bc5..d834b77714 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3984,7 +3984,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, Int128 *val) { uint64_t mask = sstatus_v1_10_mask; - uint64_t sstatus = env->mstatus & mask; + uint64_t sstatus; if (env->xl != MXL_RV32 || env->debugger) { mask |= SSTATUS64_UXL; } @@ -3995,7 +3995,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, if (env_archcpu(env)->cfg.ext_zicfilp) { mask |= SSTATUS_SPELP; } - + sstatus = env->mstatus & mask; *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); return RISCV_EXCP_NONE; } -- 2.43.0
