Hi,
I am sending this RFC for two code-generation bugs in the MIPS64 TCG host backend that are still present in QEMU 11.0.3. The first patch fixes the register order used for variable shifts and rotates. The backend currently exchanges the value and shift-count registers for the 32-bit and 64-bit SHL, SHR, SAR, and ROTR operations. A standalone AArch64 test covering all eight forms returns 0xff before the fix and 0 afterwards: https://gitlab.com/qemu-project/qemu/-/work_items/4103 The second patch preserves the address register across pre-R6 unaligned load pairs. When the qemu_ld output overlaps its dead address input, the first LWR/LWL or LDR/LDL instruction can overwrite the base needed by the second instruction. Standalone RISC-V tests for both widths fail to terminate before the fix and exit successfully afterwards: https://gitlab.com/qemu-project/qemu/-/work_items/4102 I tested both changes using clean QEMU 11.0.3 sources. The shift, unaligned-lw, and unaligned-ld tests returned 255/137/137 before the patches and 0/0/0 afterwards. The two patch files also pass scripts/checkpatch.pl without warnings. The MIPS host backend was removed from master by commits bfa0801e91ca and 586663f1fa29, so there is no corresponding master patch to submit. Would the stable maintainers consider these small fixes directly for the QEMU 11.0 branch? If a stable-only change is not appropriate here, I would appreciate guidance on how these release bugs should be handled. Thanks, Quintin --- Quintin Kong (2): tcg/mips64: Fix variable shift operand order tcg/mips64: Preserve the base of unaligned loads tcg/mips64/tcg-target.c.inc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.43.0
