On 9/8/07, Paul Brook <[EMAIL PROTECTED]> wrote: > > From DMA2.txt, NCR89C100.txt, NCR89C105.txt and turbosparc.pdf I > > gather the following: > > - CPU and IOMMU always perform slave accesses > > - Slave accesses use the 28-bit address bus to select the device > > I thought device selection was separate from the 28-bit SBus slave address > space. ie. each device has exclusive ownership of the whole 28-bit address > space, and it's effectively just multiplexing per-slave busses over a single > electrical connection.
At least the NCR slave devices use SBus bus signals for device select. I don't know whether this applies generally. > > - Slave accesses are not translated by IOMMU > > - NCR master devices (Lance, ESP) use an internal DREQ-style signal to > > indicate their need for DMA to their DMA controller > > - Master accesses use the 32-bit SBus data signals for both address and > > data - DMA controller is the master for NCR89C100+NCR89C105 combination - > > Master accesses are translated and controlled by IOMMU > > - Slave devices may or may not support master access cycles (not > > supported in the NCR case) > > - IOMMU can give direct bus access for "intelligent masters" (no devices > > known) > > > > We could model this using two buses: A slave bus between the CPU and > > the devices, and a master bus between devices and IOMMU. The slave bus > > translates the 36-bit CPU/memory bus addresses to 28-bit SBus bus > > addresses. The master bus uses IOMMU to translate 32-bit DVMA > > addresses to 36-bit CPU/memory bus addresses. Slave devices are > > connected to the slave bus and DREQs. Master devices and DMA > > controllers take the DREQs and both buses. Devices register the > > address ranges they serve on each bus. > > IIUC devices never register addresses on the master bus. The only thing that > responds on that bus is the IOMMU. Generally yes, but these "intelligent masters" and their targets would register on on both buses. The only case I can only think of is a video grabber, it's frame memory could be accessed directly by other IO devices. > > On Sun4c (without IOMMU) there would be just one bus for both purposes > > (with the MMU quirk). > > > > For the Sparc64 PCI bus which has an IOMMU, a similar dual bus > > arrangement would be needed. On PC/PPC systems the two buses would be > > again one. > > PCI shouldn't need a dual bus setup. You just have one bus for PCI and one bus > for CPU/memory. Then how would Sparc64 IOMMU intercept the device DMA? I'd think that PCI bus mastering works similarly as in SBus, or doesn't it? > IMHO the whole point of having a generic bus infrastructure is that we can > define address mapping in terms of [asymmetric] translations from one bus > address space to another. This isolates teh device from needing to care about > bridges and IOMMu. > > If we're assuming 1:1 or symmetric address space mapping there doesn't seem > much point modelling separate busses. Instead push everything into the device > registration and DMA routines. Agreed. For Sparc32/64 cases there isn't much choice, there is no symmetry.