Re: [PATCH 2/5] target/riscv: Add SiFive custom int8 matmul extension implied rules

[Daniel Henrique Barboza]

On 7/21/2026 9:20 AM, Max Chou wrote:

From: Frank Chang <frank.ch...@sifive.com>

Add SiFive custom int8 matmul extension implied rules to enable the
implied extensions of SiFive custom int8 matmul extension recursively.

Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
---
  target/riscv/cpu.c | 19 +++++++++++++++++++
  1 file changed, 19 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e643d7c7af..70baa054f9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2811,6 +2811,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
      },
  };

+static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = {

+    .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
+static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq),
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_zve32x),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
  RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
      &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
      &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
@@ -2832,6 +2850,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] 
= {
      &ZVKS_IMPLIED,  &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED,
      &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED,
      &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED,
+    &XSFVQMACCDOD_IMPLIED, &XSFVQMACCQOQ_IMPLIED,

Not related to this patch but I wonder if we should put one rule per line
in this array.  Every once in a while we have to add a rule that is
in a line that already has a lot of stuff, then we need to change multiple
lines to accommodate the new rule.


As for the patch:



Reviewed-by: Daniel Henrique Barboza <daniel.barb...@oss.qualcomm.com>

      NULL
  };