On 7/29/2026 5:39 AM, [email protected] wrote:
From: Frédéric Pétrot <[email protected]> Valid UXL field values for mstatus were restricted to fix a reported issue, but this inadvertently broke the experimental rv128 support where a value of 3 validly represents 128-bit execution. Update the mstatus write logic to permit UXL=3 when running on an rv128 CPU. Fixes: dcd028517749 ("target/riscv: Apply UXL WARL handling to vsstatus") Signed-off-by: Frédéric Pétrot <[email protected]> ---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
target/riscv/tcg/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index d834b77714..5eeb9f0e0f 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -2014,8 +2014,8 @@ static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val, RISCVMXL xl = riscv_cpu_mxl(env); uint64_t uxl = get_field(val, field);- if (uxl == MXL_RV128) {- uxl = xl == MXL_RV128 ? MXL_RV64 : xl; + if (xl != MXL_RV128 && uxl == MXL_RV128) { + uxl = xl; val = set_field(val, field, uxl); }
