Whole-register vector moves do not depend on vtype. The V-1.0 specification explicitly excludes whole-register loads, stores and moves from the vtype dependency, and Section 16.6 defines vmv<nr>r.v as a copy of the whole register group without needing to know or change vl or vtype. GEN_VMV_WHOLE_TRANS currently rejects vmv1r/2r/4r/8r when vtype.vill is set, while whole-register loads and stores already execute. Drop the vext_check_isa_ill() gate from the move translator; the RVV extension check, register-group alignment checks and vstart handling are unchanged.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4154 Signed-off-by: wangyang <[email protected]> --- target/riscv/tcg/insn_trans/trans_rvv.c.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc index fa1ee80bc59..32b54089448 100644 --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc @@ -3968,14 +3968,12 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) } /* - * Whole Vector Register Move Instructions depend on vtype register(vsew). - * Thus, we need to check vill bit. (Section 16.6) + * Whole Vector Register Move Instructions do not depend on vtype. */ #define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ { \ if (require_rvv(s) && \ - vext_check_isa_ill(s) && \ QEMU_IS_ALIGNED(a->rd, LEN) && \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ uint32_t maxsz = s->cfg_ptr->vlenb * LEN; \ -- 2.43.0
