On Fri, 2026-08-07 at 18:21 +0800, Junze Cao wrote: > The K230 SDK U-Boot SPL initializes DRAM by programming the DDRC CFG > and DDR PHY MMIO regions. The k230 machine currently exposes the DDR > configuration region as unimplemented and does not provide the PHY, > so > the SPL cannot complete the training and DFI handshakes. > > Add minimal models for the register behavior exercised by the SDK > SPL. > The controller model provides reset values, register access policy, > DFI > and software-update handshakes, and the Init-to-Normal transition. > The > PHY model provides CSR ownership, the training mailbox, and DFI > completion. Wire both devices into the k230 machine and document the > resulting SPL support. > > These device models allow firmware to complete the DDR initialization > sequence. > > Changes in v2: > > * Add LOG_UNIMP messages for unimplemented DDR PHY register accesses, > including reads returning zero and ignored writes. > > Testing performed: > > * scripts/checkpatch.pl --branch upstream/master..HEAD > * meson test -C build --print-errorlogs > qemu:qtest-riscv64/k230-ddr-test (6 subtests passed) > * Booted the K230 SDK U-Boot SPL through DDR initialization to its > SPI > boot path > > --- > Junze Cao (3): > hw/misc: Add K230 DDR controller and PHY models > hw/riscv: Connect K230 DDR controller and PHY models > tests/qtest: Add K230 DDR controller tests
Thanks! Applied to riscv-to-apply.next Alistair > > MAINTAINERS | 3 + > docs/system/riscv/k230.rst | 4 + > hw/misc/k230_ddr.c | 556 > ++++++++++++++++++++++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > hw/riscv/k230.c | 19 +- > include/hw/misc/k230_ddr.h | 59 +++++ > include/hw/riscv/k230.h | 4 + > tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++ > tests/qtest/meson.build | 3 +- > 9 files changed, 871 insertions(+), 4 deletions(-) > --- > base-commit: 3e3ccab106f879b1512f8e0d51a827dd4de30e22 > change-id: 20260807-k230-ddr-v2-f8037b6ac237 > > Best regards, > -- > Junze Cao <[email protected]> >
