On Thu, 2026-07-23 at 19:52 +0530, Abhigyan Kumar wrote:
> According to the RISC-V spec, a 64-bit system can have M-mode in 64-
> bit
> with S-mode being 32-bit (SXL bits or mstatus[35:34] being 1). In
> this
> case, read_sstatus should use SXL.
>
> QEMU doesn't allow changing the SXL bits in mstatus in M-mode. This
> was
> because of the missing MSTATUS64_SXL mask in write_mstatus. Now, both
> the SXL field in mstatus can be safely modified in M-mode and
> read_sstatus correctly uses SXL not MXL.
>
> Fixes: b550f89457 ("target/riscv: Compute mstatus.sd on demand")
> Signed-off-by: Abhigyan Kumar <[email protected]>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/tcg/csr.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 36f2004bc..a90449b87 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -2067,6 +2067,11 @@ static RISCVException
> write_mstatus(CPURISCVState *env, int csrno,
> }
>
> if (xl != MXL_RV32 || env->debugger) {
> + if ((val & MSTATUS64_SXL) != 0) {
> + mask |= MSTATUS64_SXL;
> + val = riscv_write_uxl(env, val, MSTATUS64_SXL);
> + }
> +
> if ((val & MSTATUS64_UXL) != 0) {
> mask |= MSTATUS64_UXL;
> val = riscv_write_uxl(env, val, MSTATUS64_UXL);
> @@ -4014,8 +4019,8 @@ static RISCVException
> read_sstatus(CPURISCVState *env, int csrno,
> if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
> mask |= SSTATUS_SDT;
> }
> - /* TODO: Use SXL not MXL. */
> - *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
> +
> + *val = add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask);
> return RISCV_EXCP_NONE;
> }
>
