On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote: > From: TANG Tiancheng <[email protected]> > > target/riscv/xthead.decode defines th.srri as funct6=000100 in > bits 31:26, with the 6-bit immediate in bits 25:20. > > decode_xtheadbb() switches on bits 31:25, i.e. funct6 plus imm[5]. > Therefore valid th.srri encodings are 0001000 and 0001001. The > current 0000100 and 0000101 cases use the wrong funct6 value and > decode valid th.srri instructions as illegal. > > Fix the cases to match funct6=000100 with both imm[5] values. > > Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* > instructions") > Signed-off-by: TANG Tiancheng <[email protected]> > Reviewed-by: LIU Zhiwei <[email protected]> > Reviewed-by: Daniel Henrique Barboza > <[email protected]> > Message-Id: > <20260703-b4-disas-xthead-fix-riscv-next-v4-1-84c566330...@linux.alib > aba.com>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv-xthead.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c > index fcca326d1c..2f2ddb8dd9 100644 > --- a/disas/riscv-xthead.c > +++ b/disas/riscv-xthead.c > @@ -315,8 +315,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa) > op = rv_op_th_revw; > } > break; > - case 0b0000100: > - case 0b0000101: op = rv_op_th_srri; break; > + case 0b0001000: > + case 0b0001001: > + op = rv_op_th_srri; > + break; > } > break; > case 2: op = rv_op_th_ext; break;
