On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote: > These code points are reserved with RV32. > > Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index 77347b557d..ddc2f73eae 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -3060,8 +3060,16 @@ static void decode_inst_opcode(rv_decode *dec, > rv_isa isa) > case 1: op = rv_op_c_xor; break; > case 2: op = rv_op_c_or; break; > case 3: op = rv_op_c_and; break; > - case 4: op = rv_op_c_subw; break; > - case 5: op = rv_op_c_addw; break; > + case 4: > + if (isa != rv32) { > + op = rv_op_c_subw; > + } > + break; > + case 5: > + if (isa != rv32) { > + op = rv_op_c_addw; > + } > + break; > case 6: op = rv_op_c_mul; break; > case 7: > switch ((inst >> 2) & 0b111) {
