Reviewed-by: Marco Liebel <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Brian Cain <[email protected]>
---
target/hexagon/gen_tcg_hvx.h | 62 ++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index cbf84a8caee..2a342cdee69 100644
--- a/target/hexagon/gen_tcg_hvx.h
+++ b/target/hexagon/gen_tcg_hvx.h
@@ -342,6 +342,68 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
gen_gvec_sabsdiff(MO_32, VdV_off, VuV_off, VvV_off, \
VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE)
+#define fGEN_TCG_VEC_AVG(VECE, SHIFT_FN) \
+ do { \
+ intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
+ tcg_gen_gvec_and(MO_64, tmpoff, VuV_off, VvV_off, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ SHIFT_FN(VECE, VdV_off, VdV_off, 1, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ tcg_gen_gvec_add(VECE, VdV_off, tmpoff, VdV_off, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ } while (0)
+
+#define fGEN_TCG_V6_vavgub(SHORTCODE) \
+ fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguh(SHORTCODE) \
+ fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguw(SHORTCODE) \
+ fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavgb(SHORTCODE) \
+ fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavgh(SHORTCODE) \
+ fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavgw(SHORTCODE) \
+ fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_VEC_AVGRND(VECE, SHIFT_FN) \
+ do { \
+ intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
+ tcg_gen_gvec_or(MO_64, tmpoff, VuV_off, VvV_off, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ SHIFT_FN(VECE, VdV_off, VdV_off, 1, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ tcg_gen_gvec_sub(VECE, VdV_off, tmpoff, VdV_off, \
+ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+ } while (0)
+
+#define fGEN_TCG_V6_vavgubrnd(SHORTCODE) \
+ fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguhrnd(SHORTCODE) \
+ fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguwrnd(SHORTCODE) \
+ fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavgbrnd(SHORTCODE) \
+ fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavghrnd(SHORTCODE) \
+ fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavgwrnd(SHORTCODE) \
+ fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari)
+
/* Vector shift right - various forms */
#define fGEN_TCG_V6_vasrh(SHORTCODE) \
do { \
--
2.34.1
