From: Matheus Tavares Bernardino <[email protected]>
When cpu->cfg.ieee_fp_extension is off, IEEE FP instructions don't get
executed. Let's print that info on the "-d in_asm" output to help users.
This will generate an output like the following:
0x00020e30: 0x1f82e1c0 { V0.sf = vadd(V1.sf,V2.sf) (disabled: no
ieee_fp) }
Reviewed-by: Taylor Simpson <[email protected]>
Signed-off-by: Matheus Tavares Bernardino <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Brian Cain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/1bdc772e4a795ecd9f5bf2b7e7143cc4b297318c.1776339451.git.matheus.bernard...@oss.qualcomm.com
Signed-off-by: Brian Cain <[email protected]>
---
target/hexagon/cpu_bits.h | 5 +++--
target/hexagon/printinsn.h | 2 +-
disas/hexagon.c | 4 ++--
target/hexagon/cpu.c | 5 ++++-
target/hexagon/decode.c | 4 ++--
target/hexagon/printinsn.c | 9 +++++++--
6 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 797ecabca92..a8fba4aa188 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -26,6 +26,7 @@ typedef struct HexagonCPUConfig {
uint32_t lldb_stack_adjust;
bool short_circuit;
bool ieee_fp_extension;
+ const HexagonCPUDef *hex_def;
} HexagonCPUConfig;
#define PCALIGN 4
@@ -130,7 +131,7 @@ static inline bool is_packet_end(uint32_t endocing)
return ((bits == 0x3) || (bits == 0x0));
}
-int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf,
- const HexagonCPUDef *hex_def);
+int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
+ GString *buf, const HexagonCPUConfig *cfg);
#endif
diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
index de962b5f2e6..c8389408d39 100644
--- a/target/hexagon/printinsn.h
+++ b/target/hexagon/printinsn.h
@@ -22,6 +22,6 @@
#include "insn.h"
void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
- target_ulong pc, const HexagonCPUDef *hex_def);
+ target_ulong pc, const HexagonCPUConfig *cfg);
#endif
diff --git a/disas/hexagon.c b/disas/hexagon.c
index 36b8321c26a..e2d3804606e 100644
--- a/disas/hexagon.c
+++ b/disas/hexagon.c
@@ -31,7 +31,6 @@
int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
{
- const HexagonCPUDef *hex_def = (const HexagonCPUDef *)info->target_info;
uint32_t words[PACKET_WORDS_MAX];
bool found_end = false;
GString *buf;
@@ -58,8 +57,9 @@ int print_insn_hexagon(bfd_vma memaddr, struct
disassemble_info *info)
return PACKET_WORDS_MAX * sizeof(uint32_t);
}
+ const HexagonCPUConfig *cfg = info->target_info;
buf = g_string_sized_new(PACKET_BUFFER_LEN);
- len = disassemble_hexagon(words, i, memaddr, buf, hex_def);
+ len = disassemble_hexagon(words, i, memaddr, buf, cfg);
(*info->fprintf_func)(info->stream, "%s", buf->str);
g_string_free(buf, true);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3bc2a2efa97..666b0cad532 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -444,12 +444,13 @@ static void hexagon_cpu_disas_set_info(const CPUState *cs,
const HexagonCPU *cpu = HEXAGON_CPU(cs);
info->print_insn = print_insn_hexagon;
info->endian = BFD_ENDIAN_LITTLE;
- info->target_info = HEXAGON_CPU_GET_CLASS(cpu)->hex_def;
+ info->target_info = &cpu->cfg;
}
static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ HexagonCPU *cpu = HEXAGON_CPU(dev);
HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev);
Error *local_err = NULL;
@@ -459,6 +460,8 @@ static void hexagon_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ cpu->cfg.hex_def = mcc->hex_def;
+
gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,
hexagon_hvx_gdb_write_register,
gdb_find_static_feature("hexagon-hvx.xml"));
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index e6bb7733be8..b12e91fe6a6 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -856,7 +856,7 @@ int decode_packet(DisasContext *ctx, int max_words, const
uint32_t *words,
/* Used for "-d in_asm" logging */
int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
- GString *buf, const HexagonCPUDef *hex_def)
+ GString *buf, const HexagonCPUConfig *cfg)
{
HexagonCPUDef any_def = {
.hex_version = HEX_VER_ANY, /* Allow decode to accept anything */
@@ -867,7 +867,7 @@ int disassemble_hexagon(uint32_t *words, int nwords,
bfd_vma pc,
ctx.hex_def = &any_def;
if (decode_packet(&ctx, nwords, words, &ctx.pkt, true) > 0) {
- snprint_a_pkt_disas(buf, &ctx.pkt, words, pc, hex_def);
+ snprint_a_pkt_disas(buf, &ctx.pkt, words, pc, cfg);
return ctx.pkt.encod_pkt_size_in_bytes;
} else {
for (int i = 0; i < nwords; i++) {
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
index 1673e954214..023ea12dba5 100644
--- a/target/hexagon/printinsn.c
+++ b/target/hexagon/printinsn.c
@@ -139,7 +139,7 @@ static void snprintinsn(GString *buf, Insn *insn)
}
void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
- target_ulong pc, const HexagonCPUDef *hex_def)
+ target_ulong pc, const HexagonCPUConfig *cfg)
{
bool has_endloop0 = false;
bool has_endloop1 = false;
@@ -171,12 +171,17 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt,
uint32_t *words,
}
g_string_append(buf, "\t");
- if (opcode_supported(pkt->insn[i].opcode, hex_def)) {
+ if (opcode_supported(pkt->insn[i].opcode, cfg->hex_def)) {
snprintinsn(buf, &(pkt->insn[i]));
} else {
g_string_append(buf, "<invalid>");
}
+ if (!cfg->ieee_fp_extension &&
+ GET_ATTRIB(pkt->insn[i].opcode, A_HVX_IEEE_FP)) {
+ g_string_append(buf, " (disabled: no ieee_fp)");
+ }
+
if (i < pkt->num_insns - 1) {
/*
* Subinstructions are two instructions encoded
--
2.34.1
