On 8/12/2026 2:44 PM, Max Chou wrote:
From: Frank Chang <[email protected]> Add SiFive custom int8 matmul extension implied rules to enable the implied extensions of SiFive custom int8 matmul extension recursively. Signed-off-by: Frank Chang <[email protected]> Signed-off-by: Max Chou <[email protected]> ---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
target/riscv/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fffb92ff110..265a92a8b7f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2811,6 +2811,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = { }, };+static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = {+ .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, @@ -2862,6 +2880,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { &SMCTR_IMPLIED, &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, + &XSFVQMACCDOD_IMPLIED, + &XSFVQMACCQOQ_IMPLIED, NULL };
