One of my pet peeves is the non-automatic addition of indexes to rv_op
which must match entries in rvi_opcode_data[].
Reorganize the disassembler to pass around pointers to individual opcodes
rather than pointer to table + index. To do that, rewrite how pseudo ops
are processed, replacing indexes with pointers. Merge the decompression
of compressed opcodes into the pseudo ops mechanism.
Fix quite a few bugs found in the process, mostly related to isa level.
Changes for v2:
- Rebase on riscv-to-apply.next, which now contains Tiancheng's fixes.
- Adjust the DECOMP macro to make clang happy.
- new patch: "disas/riscv: Skip post-processing of illegal insns"
The only unreviewed patch is the new one.
r~
Richard Henderson (52):
disas/riscv: Move operand extractors earlier in file
disas/riscv: Reduce rv_insn to uint32_t
disas/riscv: Tidy dec initialization in disasm_inst
disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands
disas/riscv: Pass rv_opcode_data pointer to/from
decode_inst_decompress
disas/riscv: Pass rv_opcode_data pointer to/from
decode_inst_lift_pseudo
disas/riscv: Pass rv_opcode_data pointer to format_inst
disas/riscv: Tidy disasm_inst main loop
disas/riscv: Set dec->opcode_data in decode function
disas/riscv: Drop explicit zero of rv_opcode_data fields
disas/riscv: Drop useless const in structures
disas/riscv: Drop codec from rv_decode
disas/riscv: Handle c.addi4spn imm != 0 during decode
disas/riscv: Simplify c.addi
disas/riscv: Handle c.lui imm != 0 during decode
disas/riscv: Handle c.{srli,srai} imm during decode
disas/riscv: Handle c.slli imm != 0 during decode
disas/riscv: Do not recognize c.{addw,subw} with rv32
disas/riscv: Remove rvcd_imm_nz
disas/riscv: Unify decomp_rv{32,64,128}
disas/riscv: Drop always true branch pseudos
disas/riscv: Handle aliases of csrrw during decode
disas/riscv: Handle aliases of csrrs during decode
disas/riscv: Handle aliases of csrrwi during decode
disas/riscv: Break pseudo loop for jal and jalr
disas/riscv: Allow decode_inst_lift_pseudo to loop
disas/riscv: Handle decompression via decode_inst_lift_pseudo
disas/riscv: Drop format from DECOMP insns
disas/riscv: Tidy rv_comp_data terminators
disas/riscv: Chain "ret" pseudo off "jr" pseudo
disas/riscv: Chain "nop" pseudo off "mv" pseudo
disas/riscv: Use rv_codec_illegal for pseudos
disas/riscv: Simplify some insn decompressions
disas/riscv: Store op pointer in rv_comp_data
disas/riscv: Return rv_opcode_data pointer from decoders
disas/riscv: Skip post-processing of illegal insns
disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32
disas/riscv: Fix rv32 encoding of zext.h
disas/riscv: Fix isa decoding of rev8
disas/riscv: Fix typo in th.lbib format
disas/riscv: Split ventana_opcode_data
disas/riscv: Split xlrbr_opcode_data
disas/riscv: Split xthead_opcode_data
disas/riscv: Move rv_op_illegal to riscv.c
disas/riscv: Split out riscv-op.c.inc
disas/riscv: Merge all mop.r.n to one pattern
disas/riscv: Merge all mop.rr.n to one pattern
disas/riscv: Merge all c.mop.n to one pattern
disas/riscv: Tidy decode of c.mop.n
disas/riscv: Tidy decode of mop.r.n and mop.rr.n
disas/riscv: Split rvi_opcode_data
disas/riscv: Sort riscv-op.c.inc
disas/riscv-xlrbr.h | 4 +-
disas/riscv-xthead.h | 24 +-
disas/riscv-xventana.h | 4 +-
disas/riscv.h | 46 +-
disas/riscv-xlrbr.c | 57 +-
disas/riscv-xthead.c | 503 +--
disas/riscv-xventana.c | 23 +-
disas/riscv.c | 6390 +++++++++++----------------------
disas/riscv-op.c.inc | 913 +++++
disas/riscv-xlrbr-op.c.inc | 8 +
disas/riscv-xthead-op.c.inc | 125 +
disas/riscv-xventana-op.c.inc | 2 +
12 files changed, 3411 insertions(+), 4688 deletions(-)
create mode 100644 disas/riscv-op.c.inc
create mode 100644 disas/riscv-xlrbr-op.c.inc
create mode 100644 disas/riscv-xthead-op.c.inc
create mode 100644 disas/riscv-xventana-op.c.inc
--
2.43.0
