On 13/08/26, Joel Stanley wrote:
> The register values lost their leading zeroes when the underlying type
> was changed, resulting in mismatched padding and harder to read output.
>
> Print with a runtime field width based on MXL, so values are 16 hex
> digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
> adding target_ulong back into the dump.
>
> Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
> Signed-off-by: Joel Stanley <[email protected]>
> ---
> before:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp
> ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0 x7/t2
> 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 708 x10/a0 270f x11/a1 8
> x12/a2 0 x13/a3 120 x14/a4 14992a1 x15/a5 ffffffffffffffff
> x16/a6 fffff079 x17/a7 79 x18/s2 0 x19/s3 7d0
> x20/s4 ffffffff805ca228 x21/s5 31 x22/s6 ff60000000e15000 x23/s7
> ffffffff804228c8
> x24/s8 0 x25/s9 ffffffff804e3e90 x26/s10 0 x27/s11 0
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5
> ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2
> ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6
> ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0
> ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4
> ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2
> ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6
> ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10
> ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10
> ffffffff00000000 f31/ft11 ffffffff00000000
>
> after:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0000000000000000 x1/ra ffffffff803f10f6 x2/sp
> ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1
> 0000000000000000 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 0000000000000e10 x10/a0
> 000000000000270f x11/a1 0000000000000008
> x12/a2 0000000000000000 x13/a3 0000000000000120 x14/a4
> 0000000002575fd6 x15/a5 ffffffffffffffff
> x16/a6 00000000fffff079 x17/a7 0000000000000079 x18/s2
> 0000000000000001 x19/s3 0000000000000ed8
> x20/s4 ffffffff805ca228 x21/s5 0000000000000060 x22/s6
> ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0000000000000000 x25/s9 ffffffff804e3e90 x26/s10
> 0000000000000000 x27/s11 0000000000000000
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5
> ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2
> ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6
> ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0
> ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4
> ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2
> ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6
> ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10
> ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10
> ffffffff00000000 f31/ft11 ffffffff00000000
>
> I also wrote a patch to align the first column of register values, but
> that creates the dilemma between aligning the numbers vs keeping the
> spacing between the registers and their value within a row. Aside from
> avoiding bikeshedding, it wastes more columns for an already wide
> output, so opted not to 'fix' that.
>
> Signed-off-by: Joel Stanley <[email protected]>
> ---
> target/riscv/cpu.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Nice, thank you!:)
Reviewed-by: Anton Johansson <[email protected]>
